Control store

A control store is a specialized memory unit within a central processing unit (CPU) that contains the microcode or microprogram used to control the operation of the CPU's datapath and other internal components. It is a fundamental component of a microprogrammed control unit, which interprets machine instructions by executing a sequence of simpler micro-operations stored in the control store.

Historical Context and Purpose

The concept of the control store emerged in the 1950s and became prevalent in the design of complex instruction set computers (CISC) during the 1960s and 1970s. Before its adoption, CPU control logic was typically implemented using hardwired circuits composed of discrete logic gates, flip-flops, and counters. While fast, hardwired control became exceedingly complex, difficult to design, and nearly impossible to modify for new instructions or to correct design flaws. The control store introduced a software-like layer of abstraction. By storing the control signals for each micro-operation in a memory array, designers could create and update the CPU's control logic by modifying the contents of this memory (the microcode), rather than redesigning physical circuits. This made CPUs more flexible, easier to debug, and capable of supporting sophisticated instruction sets, including those with complex addressing modes and multi-step operations.

Architecture and Operation

In a microprogrammed CPU, the control unit is itself a simple computer. The control store is its read-only memory (ROM), though modern implementations may use writable control stores (WCS). Each word in the control store is a microinstruction, which contains bit fields that directly or indirectly control the various multiplexers, registers, arithmetic logic units (ALUs), and buses within the CPU's datapath. The execution of a single machine instruction (e.g., ADD or MOVE) is broken down into a sequence of microinstructions, forming a microprogram.

The operation follows a cycle: The microprogram counter (µPC) or microsequencer holds the address of the next microinstruction to be fetched from the control store. After a microinstruction is fetched and decoded, its control bits activate specific datapath components for one clock cycle. Simultaneously, the microinstruction contains fields that determine the next µPC value, which may be an increment, a branch based on a condition (like an ALU status flag), or a jump to a specific micro-routine. This process continues until the machine instruction's microprogram completes, at which point the main instruction fetch unit supplies the next machine instruction, and its opcode is used as an initial index into the control store to begin the corresponding microprogram.

Types of Control Stores

Control stores are traditionally implemented using ROM due to its non-volatility and speed. However, variations exist:

• Read-Only Memory (ROM): Used in finalized designs where the microcode is permanently fixed during manufacturing.
• Programmable Read-Only Memory (PROM) & Erasable PROM (EPROM): Allow for post-manufacture programming, useful for prototyping and field updates in some older systems.
• Writable Control Store (WCS): Uses RAM instead of ROM, allowing the microcode to be dynamically loaded, typically by the operating system during boot. This provides maximum flexibility for patching CPU logic or emulating other instruction sets. Some historical mainframes and modern processors for virtualization support WCS features.

Microinstruction Format

The format of a microinstruction can be horizontal or vertical, which directly impacts the width and depth of the control store.

• Horizontal Microcode: Each microinstruction has many independent bit fields, allowing it to control multiple datapath operations in parallel within a single clock cycle. This results in very wide control store words (e.g., 64 to 128 bits or more) but shorter microprograms (fewer total microinstructions). It offers high performance but consumes more silicon area for the wide memory.
• Vertical Microcode: Microinstructions resemble simple machine instructions themselves. They are narrower (e.g., 16-32 bits) and encode operations in a more compact, sometimes sequential manner. A vertical microinstruction might specify a single operation (e.g., "ALU add"), requiring multiple cycles to perform what horizontal microcode does in one. This leads to deeper microprograms (more microinstructions) but a smaller, cheaper control store.

Many designs use a compromise, known as diagonal microcode, which incorporates features of both.

Modern Relevance and Evolution

While microprogramming with a dedicated control store was ubiquitous in classic CISC processors (e.g., IBM System/360, Motorola 68000, Intel x86 up to the 486), the rise of reduced instruction set computing (RISC) in the 1980s championed a return to simpler, hardwired control units for maximum speed. Most modern high-performance RISC and RISC-inspired cores (e.g., ARM, RISC-V, Apple Silicon, AMD Zen, Intel Core) use hardwired control for the vast majority of instructions.

However, the control store concept persists in several key areas:

1. Complex x86 Processors: Modern x86 CPUs from Intel and AMD use a hybrid approach. A front-end decodes complex x86 instructions into simpler internal RISC-like operations (micro-ops). This translation process is often implemented via microcode stored in a control store. The microcode also handles complex instructions, exception handling, and serves as a patch mechanism for errata.
2. Microcode Update Mechanisms: Modern CPUs include a writable control store area that can be updated by the BIOS/UEFI or operating system to apply critical bug fixes and security patches without altering the physical hardware.
3. System Firmware and Boot Code: The principles of a control store are analogous to firmware stored in ROM or flash memory that initializes and controls complex hardware subsystems.
4. Education and Prototyping: Microprogrammed control units with a control store remain a valuable pedagogical tool for teaching computer architecture, as they clearly separate the datapath from the control logic.

Thus, while the classical, large control store as the primary CPU controller has diminished in favor of hardwired logic for performance-critical paths, the underlying concept remains vital for managing complexity, ensuring compatibility, and providing a crucial layer of firmware-based control in contemporary processors.